In clocked systems, data frequently has to be interchanged between two different circuit blocks. The individual circuit blocks may in this case, for example, interchange data which is then processed further in the respective circuit blocks. The two circuit blocks are each clocked with a clock signal at the same frequency. In order to avoid data errors during the data interchange, the data interchange must be carried out synchronously, that is to say the data to be interchanged must always be applied to the circuit blocks at the correct times.
Because the circuit blocks are arranged at different locations, delay-time differences can occur between the two clock signals from the circuit blocks. Lines of different lengths for the two clock signals likewise lead to delay-time differences. A delay-time difference results in a phase difference between the clock signals from the two circuit blocks. In addition, an unknown phase difference between the two clock signals is caused by a slight random variation, which is referred to as “a jitter” and by different frequency-processing measures. If the frequencies of the clock signal are the same, but originate from different signal sources, then the phase angles between them are generally unknown.
When data is being interchanged, a circuit block emits the data to be interchanged at its output during one clock cycle, for example on a rising flank of its clock signal. The second circuit block reads the data applied to its input, for example on a rising clock flank of its clock signal, and processes this data further. Because of the phase difference between the two clock signals in the circuit blocks, the production at the data output and the reading process at the data input each take place at different times. It is thus possible for a read cycle to have already started before the first circuit block has produced the data to be transferred at its data output. This results in a loss of data, and thus to an error in the data transmission between the blocks.
In order to avoid such loss of data, synchronization circuits and, in particular, so-called FIFO buffers (FIFO=First-in, First-out) are connected between the individual circuit blocks. The buffer circuits temporarily store the data to be transferred in flipflop circuits, and emit it again when required. In this case, the data that is the first to be stored in the buffer is also the first data that is output again.
FIG. 3 shows one example of a synchronous interface with a FIFO buffer. The synchronization circuit 3 is in this case connected between the two circuit blocks 1 and 2. The circuit block 1 emits a data word at its output during each clock period of its clock signal. The data word comprises one or more data items and is stored in one of the three parallel-connected register banks 32. The register banks 32 in this case each have a plurality of parallel-connected flipflop circuits, which each store one data item from the data word. The selection of which of the three register banks 32 is used to store the data word of the circuit block 1 is made by the control device 31. The stored data word is read via a multiplexer unit 33, which uses a control signal from the control unit 31 to connect one of the three register banks 32 to the output of the synchronization circuit 3, and thus supplies the data word to the second circuit block 2. In this case, the data word is emitted in the sequence in which it was also stored in the register banks 32.
After the process of reading from a data bank and production at the second circuit block, the contents of the register bank are deleted, and this register bank is enabled for another writing process again. The reading and writing processes are synchronized via the control device 31, to which the clock signals from the circuit block 1 and from the circuit block 2 are supplied.
If the data reading and writing processes are carried out using two different clock signals at the same frequency, there must be at least three memory locations for each data item to be synchronized. 3*N memory locations are therefore required for synchronization of n parallel data items which form a data word. Each of the described register banks 32 thus contains n memory locations. The third register bank is required in order to ensure that major fluctuations in the phase angle between the clock signal of the first circuit block and the clock signal of the second circuit block are coped with in both the positive and negative directions. Particularly in the case of circuit blocks whose data word to be synchronized comprises a very large number of parallel data items, the need for a third memory location per data item in the synchronization circuit leads to a large number of memory locations. This increases the space requirements and results in additional costs.